Anthropic is seeking a Research Engineer for its Code RL team within the AI Research & Engineering department. The role focuses on leveraging chip design expertise to build reinforcement learning environments that enable silicon design and optimization. Key responsibilities include inventing and implementing RL environments for RTL generation, design verification, and physical design optimization; optimizing EDA-tool latency; shaping the research roadmap; delivering work to research and production training runs; and collaborating with researchers and engineers across the organization. Candidates should have expertise in ASIC or FPGA design, EDA tools, and chip tape-out experience, as well as a passion for AI safety. The position is hybrid, based at the San Francisco office, and offers a competitive salary range of USD 500,000–850,000.
Research Engineer, Chip Design RL (Reinforcement Learning) at Anthropic
Hybrid - San Francisco, CA, United States
More jobs at AnthropicSalary
USD 500,000 - 850,000
Requirements
Skills
- Expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
- Fluent with industry EDA tools and processes.
- Taped out chips and have experience going from spec to silicon.
- Know how to balance research exploration with engineering implementation.
- Passionate about AI's potential and committed to developing safe and beneficial systems.
- Bachelor’s degree or equivalent combination of education, training, and/or experience.
- Field relevant to the role as demonstrated through coursework, training, or professional experience.
- Experience with reinforcement learning, evaluations or environments.
- Built tooling or automation around chip design flows.
- Worked on ML accelerators or high-performance compute hardware.
- Familiarity with high-level synthesis or architecture simulators.
Responsibilities
- Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal verification), and physical design optimization.
- Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
- Conduct experiments and shape our roadmap.
- Deliver your work into research and production training runs.
- Collaborate with other researchers and engineers across and outside Anthropic.
Technologies
ASICFPGARTLUVMformal methodscoverage-driven verificationEDA toolssynthesisplace-and-routetiming closurePPA optimizationDFTECOsreinforcement learningML acceleratorshigh-performance compute hardwarehigh-level synthesisarchitecture simulators
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